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In this paper, we describe the performance elements used in our 28nm bulk devices with the gate first high-k/metal gate scheme for high performance applications. By using the innovative stressor integrations including improved stress memory technique (SMT), optimized embedded SiGe process and dual stress liner, Ieff of ~540/360 uA/um have been obtained for NMOS and PMOS respectively with the gate...
To achieve an ultra-shallow junction formation with low resistivity, Cluster Carbon (CC) co-implantation for NMOS source drain and source drain extension condition are investigated. It is found that using CC co-implantation, Phosphorus (P) TED was suppressed and the lower junction depth Xj is achieved. The sheet resistivity Rs is increased with the increment of the Carbon dose, but the Rs×Xj product...
A Constant-gm CMOS op-amp with Rail-to-Rail input and output stage is proposed in this paper. It is based on a novel configuration that consists of four MOSFETS as dummy differential pairs to select different differential pair as input pair, according to the different common-mode voltage. The constant gm is accomplished by avoiding the input NMOS and PMOS differential pairs operating synchronously,...
SRAM sense amplifier plays a key role in memory design. With technology scaling to the nanometer, the device mismatch increases and the distribution effect induces unstable signal injection, thus affecting the reliability of memory system. This paper presents a new method for SRAM sense amplifier design. It incorporates reasonable delay between the passgate and enable signals to effectively mitigates...
Abstract A small footprint active clamp design with low voltage CMOS and high voltage BJT components in complementary BiCMOS process is proposed, analyzed by simulation and experimentally validated. The new clamp is composed from stacked NMOS driver to achieve appropriate voltage tolerance and power BJT. Both NPN and PNP- based versions of the clamp are compared to the stacked NMOS clamp.
This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s...
High-quality germanium oxynitride (GeON) gate dielectrics for Ge-based metal-oxide-semiconductor (MOS) devices were fabricated by plasma nitridation of ultrathin thermal oxides on Ge(100) substrates. Although ultrathin oxides with abrupt GeO2/Ge interfaces can be formed by conventional dry oxidation, air exposure results in serious electrical degradation. It was found that plasma nitridation forms...
As the MOSFET's channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to doping fluctuation in the channel region. In this paper, a novel highly stable 10T SRAM cell is proposed which eliminates read SNM during read and write operation...
This paper proposed an advanced logarithm cofactor difference operator (LogCDO) method to extract parameters of the MOS devices' post-breakdown current. The experimental results of the post breakdown current in MOS devices at different temperature are used to demonstrate the validity of the advanced LogCDO method. The post-breakdown current is equivalent to a dual diode circuit model, and then the...
Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching...
We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.
This paper reports modeling the parasitic bipolar device in the 40 nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0 V to 2 V at the gate, the case with a slower rise time shows a faster turn-on in the...
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